The TEST1 and TEST0 bits are intended to allow the user to force all output and I/O pins to a known state, either all high, all low, or tri-state. For DS26502 revisions A2 and C1, the function of these bits are suppressed by the operating mode that the part is configured for, so that any output pins that are tri-stated based on the operating mode selected are still tri-stated regardless of the setting of the TEST1 and TEST0 bits. The affected operating modes and the associated pins are shown in the table below. The pins shown in the table will not be forced into the state indicated by the TEST1 and TEST0 bits and will instead remain tri-stated. Table 1. There is no fix or work-around for this issue.
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Keywords: DS26502
